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TPS23757
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SLVS948D – JULY 2009 – REVISED NOVEMBER 2013
DT
Dead-time programming sets the delay between GATE and GAT2 to prevent overlap of MOSFET ON times as
shown in Figure 2 . GAT2 turns the second MOSFET OFF when it transitions high. Both MOSFETs should be
OFF between GAT2 going high to GATE going high, and GATE going low to GAT2 going low. The maximum
GATE ON time is reduced by the programmed dead-time period. The dead time period is specified with 1 nF of
capacitance on GATE and GAT2. Different loading on these pins will change the effective dead time.
A resistor connected from DT to ARTN sets the delay between GATE and GAT2 per Equation 3 .
t DT ( )
R DT ( kW ) =
2
ns
(3)
Connect DT to V B to set the dead time to 0 and turn GAT2 OFF.
FRS
Connect a resistor from FRS (frequency and synchronization) to ARTN to program the converter switching
frequency. Select the resistor per the following relationship.
R FRS (k W ) =
17250
f SW (kHz)
(4)
? V
ADPTR_ON - V PPDEN
R PPD1 = ? ÷
The converter may be synchronized to a frequency above its maximum free-running frequency by applying short
ac-coupled pulses into the FRS pin per Figure 25 .
The FRS pin is high impedance. Keep the connections short and apart from potential noise sources. Special care
should be taken to avoid crosstalk when synchronizing circuits are used.
GATE
Gate drive output for the dc/dc converter’s main switching MOSFET. GATE’s phase turns the main switch ON
when it transitions high, and OFF when it transitions low. GATE is held low when the converter is disabled.
GAT2
GAT2 is the second gate drive output for the dc/dc converter. GAT2’s phase turns the second switch OFF when
it transitions high, and ON when it transitions low. This drives flyback synchronous rectifiers per Figure 1 . See
the DT Pin Description for GATE to GAT2 timing. Connecting DT to V B disables GAT2 in a high-impedance
condition. GAT2 is low when the converter is disabled.
PPD
PPD is a multifunction pin that has two voltage thresholds, PPD1 and PPD2.
PPD1 permits power to come from an external low voltage adapter, e.g., 24 V, connected from V DD to V SS by
over-riding the normal hotswap UVLO. Voltage on PPD above 1.55 V (V PPDEN ) enables the hotswap MOSFET,
inhibits class current, and enables APb. A resistor divider per Figure 30 provides ESD protection, leakage
discharge for the adapter ORing diode, reverse adapter protection, and input voltage qualification. Voltage
qualification assures the adapter output voltage is high enough that it can support the PD before it begins to draw
current.
? ?
÷
? V PPDEN ÷
? + I PPD ÷
è R PPD2 ?
? ( V PPDEN - V PPDH )
V ADPTR_OFF = ( V PPDEN - V PPDH ) + ê R PPD1 ′ ?
? ÷ ú
ê ?
è ? ?
é ? ù
R PPD2
+ I PPD ÷ ú
(5)
PPD2 enables normal class regulator operation when V PPD is above 8.3 V to permit normal classification when
APD is used in conjunction with diode D VDD (see Figure 29 ). Tie PPD to V DD when PPD2 operation is desired.
Copyright ? 2009–2013, Texas Instruments Incorporated
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